With the development of the electrical technology, a FET, such as a complementary metal-oxide semiconductor (CMOS) transistor, with high integrity and operation speed is required. As each technology nodes shrink, the dimensions of a CMOS and the thickness of its gate oxide, however, must be reduced and gate leakage could be more likely triggered by the reduced gate length.
In order to reduce gate leakage, high dielectric constant (high-k) gate insulator layers are used and the conventional dummy gate electrode is replaced with a metal gate (MG) electrode to improve the device performance as the feature sizes has being decreased.
The conventional technique for fabricating a metal gate CMOS transistor includes the following steps: Firstly a CMOS transistor including a PMOS and an NMOS each having a poly-silicon dummy gate electrode is formed. After the CMOS transistor is completed, the dummy gate electrodes of the NMOS and the PMOS will be removed by an etching process. Subsequently, various work function layers and two MG electrodes are successively deposited in the region where the dummy gate electrodes of the NMOS and the PMOS were originally located, while the metal gate CMOS transistor is formed.
Because NMOS and the PMOS require different work function layers with diverse work function values, and the different work function layers may interference with each other, thus an etching process is performed by the prior art to remove the portion of the PMOS's work function layer which is deposited on the NMOS before the NMOS's work function layer is deposited, and thus an etching stop layer consisting of tantalum nitride (TaN) deposited under the PMOS's work function layer is provided to protect the underlying high-k gate insulator layer from being damaged by the etching process.
However, since the TaN may adversely affect the performance of the PMOS's work function layer, thus the thickness of the etching stop layer should be minimized, and is always a trade-off between the etching residue and the etching stop layer punch through. Therefore, it is necessary to provide an advanced semiconductor device and the fabrication method thereof to obviate the drawbacks and problems encountered from the prior art.